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Träfflista för sökning "db:Swepub ;pers:(Jantsch Axel);srt2:(2005-2009);pers:(Weerasekera Roshan)"

Sökning: db:Swepub > Jantsch Axel > (2005-2009) > Weerasekera Roshan

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1.
  • Grange, Matt, et al. (författare)
  • Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
  • 2009
  • Ingår i: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION. - San Francisco : IEEE conference proceedings. - 9781424445110 ; , s. 345-351
  • Konferensbidrag (refereegranskat)abstract
    • The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.
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2.
  • Weldezion, Awet Yemane, et al. (författare)
  • Scalability of Network-on-Chip Communication Architecture for 3-D Meshes
  • 2009
  • Ingår i: 2009 3RD ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP. - NEW YORK : IEEE. - 9781424441426 ; , s. 114-123
  • Konferensbidrag (refereegranskat)abstract
    • Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologiesfor 3-D Network-on-Chips (NoC) using Through-Silicon-Was (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3-D NoC is examined under both communication architectures and compared to 2-D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.
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Weerasekera, Ros... (2)Ta bort avgränsningen
Weldezion, Awet Yema ... (2)
Jantsch, Axel (2)Ta bort avgränsningen
Lu, Zhonghai (2)
Pamunuwa, Dinesh (2)
Grange, Matt (2)
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Tenhunen, Hannu (1)
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2009 (2)

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